Much solid state circuitry now is provided by an appropriately interconnected array of logic gates formed by one of the state-of-the-art integrated circuit technologies such as CMOS, NMOS or bipolar. The cells making up the individual gates of such a gate array are basically identical. It is only the interconnections between the various gates which differentiate one digital logic circuit from another. The circuit designer provides a desired circuitry implementation, merely by controlling the interconnects between the various gate cells. The use of gate arrays simplifies and accelerates the manufacturing process.
Utilization of logic gate arrays, though, is not without its problems. A circuit designer basically has no control over the parameters of the individual cells. Thus, it generally is not possible to "tweak" a gate array of this type by, for example, changing device parameters and layout parameters to alleviate problems with synchronization, as one can do if the circuit is a customized monolithic integrated circuit.
The inability of the circuit designer to "tweak" a circuit to obtain optimum performance has limited the use of logic gate array arrangements for various purposes. For example, phase-locked-loop circuits used to assure a desired phase and frequency of a signal, rely for operation on comparison of an output signal of a voltage control oscillator with a reference signal. The phase and frequency of the output signal is then adjusted to conform to the phase and frequency of the reference signal.
A main element of prior art phase-locked-loop circuit is a phase comparator (sometimes referred to as a phase "detector"). A phase comparator is used to compare the requisite reference signal to the output of the voltage controlled oscillator. Such a comparator typically has one of two configurations: (a) "type-I" phase comparator, and a "type-II" phase comparator. A type-I phase comparator is an exclusive-OR network which operates in a manner analogous to an over-driven analog balanced mixer. A type-II phase comparator is an edge-controlled, digital memory network typically comprising four flip-flop stages, control gating and a three-state output circuit. Such a phase comparator reacts only to the edges of a reference signal and a signal representative of an error, so that the duty cycles of the signals are irrelevant.
Type-II phase comparators for phase-locked-loops have been designed for custom monolithic circuitry. For example, a typical one may be found in the CMOS Integrated Circuit Manual (1980) published by RCA, pages 714-717 ("The RCA CMOS/MOS Phase-Locked-Loop: A Versatile Building Block for Micro-Power Digital and Analog Applications"). However, such phase comparators are not appropriately implementable in gate arrays. Due to unexpected circuit response caused by propagation and triggering delays, some of the components of phase comparators implemented by gate arrays may have outputs which conflict with the outputs of other phase comparator components. The result can be a logic decision error, causing the phase comparator to generate a large, incorrect error signal for one or more periods of the signals whose frequency and phase are being compared. The stability and response time of the phase-locked-loop suffers as a result of such operational errors of the phase comparator.
Another problem typically associated with type-II phase comparators implemented in a gate array structure, is latch-up upon start-up. When the phase-locked-loop is first powered on, it is possible that two mutually-exclusive internal control signals could be produced simultaneously. For instance, it is possible for the Q and Q of a flip-flop to go high simultaneously, thus placing the flip-flop in an indeterminate state. Generally, extra logic is required to ensure that either this indeterminate state never can occur, or that the flip-flop can be reset out of this state if it does occur.